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EP2AGZ300FF35I4N 554 I/O 11920 LABs ALTERA FPGA Chip

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EP2AGZ300FF35I4N 554 I/O 11920 LABs ALTERA FPGA Chip

Name: EP2AGZ300FF35I4N 554 IO 11920 LABs ALTERA FPGA Chip
Brand: Intel / Altera
Price: 4000 USD

Brand Name : Intel / Altera

Model Number : EP2AGZ300FF35I4N

Certification : Lead free / RoHS Compliant

MOQ : 1 pcs

Price : USD 4000-5500 pcs

Payment Terms : T/T, Western Union, Paypal, Trade Assurance, Credit Card

Supply Ability : 126 pcs

Delivery Time : 3-5 Day

Packaging Details : International Standard Packaging

Category : IC FPGA

Condition : Original 100%,Brand New and Original,New

Series : Arria II GZ

Number of Logic Array Blocks - LABs : 11920

Number of I/Os : 554 I/O

Operating Supply Voltage : 1.5 V to 3.3 V

Package / Case : FBGA-1152

Data Rate : 600 Mb/s to 6.375 Gb/s

Service : BOM Kitting

Lead time : In Stock,contact us

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EP2AGZ300FF35I4N ALTERA FPGA Chip FBGA-1152 554 I/O Arria II GZ

Product Attribute	Attribute Value
Manufacturer:	Intel
Product Category:	FPGA - Field Programmable Gate Array
Product:	Arria II GZ
Number of Logic Elements:	298000
Number of Logic Array Blocks - LABs:	11920
Number of I/Os:	554 I/O
Operating Supply Voltage:	1.5 V to 3.3 V
Minimum Operating Temperature:	- 40 C
Maximum Operating Temperature:	+ 85 C
Mounting Style:	SMD/SMT
Package / Case:	FBGA-1152
Packaging:	Tray
Data Rate:	600 Mb/s to 6.375 Gb/s
Series:	Arria II GZ
Brand:	Intel / Altera
Embedded Block RAM - EBR:	3725 kbit
Maximum Operating Frequency:	540 MHz
Moisture Sensitive:	Yes
Number of Transceivers:	16/24 Transceiver
Product Type:	FPGA - Field Programmable Gate Array
Factory Pack Quantity:	24
Subcategory:	Programmable Logic ICs
Total Memory:	18413 kbit
Tradename:	Arria
Part # Aliases:	971029

Arria II GX devices have dedicated configuration banks at Bank 3C and 8C, which support dedicated configuration pins and some of the dual-purpose pins with a
configuration scheme at 1.8, 2.5, 3.0, and 3.3 V. For Arria II GZ devices, the dedicated configuration pins are located in Bank 1A and Bank 1C. However, these
banks are not dedicated configuration banks; therefore, user I/O pins are available in Bank 1A and Bank 1C.

Dedicated VCCIO, VREF, and VCCPD pin per I/O bank to allow voltage-referenced I/O standards. Each I/O bank can operate at independent VCCIO, VREF, and
VCCPD levels.

Auto-Calibrating External Memory Interfaces
■ I/O structure enhanced to provide flexible and cost-effective support for different types of memory interfaces
■ Contains features such as OCT and DQ/DQS pin groupings to enable rapid and robust implementation of different memory standards
■ An auto-calibrating megafunction is available in the Quartus II software for DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM, RLDRAM II memory interface
PHYs; the megafunction takes advantage of the PLL dynamic reconfiguration feature to calibrate based on the changes of process, voltage, and temperature (PVT).

EP2AGZ300FF35I4N 554 I/O 11920 LABs ALTERA FPGA Chip

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EP2AGZ300FF35I4N 554 I/O 11920 LABs ALTERA FPGA Chip

EP2AGZ300FF35I4N 554 I/O 11920 LABs ALTERA FPGA Chip

EP2AGZ300FF35I4N Arria II GZ

11920 LABs Arria II GZ

554 I/O ALTERA FPGA Chip

EP2AGZ300FF35I4N 554 I/O 11920 LABs ALTERA FPGA Chip Images